NXP Semiconductors LPC1768 - Uartn Fractional Divider Register (U0 FDR - 0 X4000 C028, U2 FDR - 0 X4009 8028, U3 FDR - 0 X4009 C028)

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User manual Rev. 3 — 19 December 2013 313 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
The PulseDiv bits in UnICR are used to select the pulse width when the fixed pulse width
mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs. Table 284
shows the
possible pulse widths.
14.4.12 UARTn Fractional Divider Register (U0FDR - 0x4000 C028, U2FDR -
0x4009 8028, U3FDR - 0x4009 C028)
The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for
the baud rate generation and can be read and written at the user’s discretion. This
pre-scaler takes the APB clock and generates an output clock according to the specified
fractional requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be greater than 2.
2 FixPulseEn When 1, enabled IrDA fixed pulse width mode. 0
5:3 PulseDiv Configures the pulse when FixPulseEn = 1. See text below for details. 0
31:6 - NA Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
0
Table 283: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit
description …continued
Bit Symbol Value Description Reset value
Table 284: IrDA Pulse Width
FixPulseEn PulseDiv IrDA Transmitter Pulse width (µs)
0 x 3 / (16  baud rate)
102
 T
PCLK
114  T
PCLK
128  T
PCLK
1 3 16  T
PCLK
1 4 32  T
PCLK
1 5 64  T
PCLK
1 6 128  T
PCLK
1 7 256  T
PCLK
Table 285: UARTn Fractional Divider Register (U0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR -
0x4009 C028) bit description
Bit Function Value Description Reset value
3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0, fractional
baud-rate generator will not impact the UARTn baudrate.
0
7:4 MULVAL 1 Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for
UARTn to operate properly, regardless of whether the fractional baud-rate
generator is used or not.
1
31:8 - NA Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
0