UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 689 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.5.6.3 Restrictions
You can use SP and PC only in the
MOV
instruction, with the following restrictions:
• the second operand must be a register without shift
• you must not specify the S suffix.
When Rd is PC in a
MOV
instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
Remark: Though it is possible to use
MOV
as a branch instruction, ARM strongly
recommends the use of a
BX
or
BLX
instruction to branch for software portability to the ARM
instruction set.
34.2.5.6.4 Condition flags
If S is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see Section 34.2.3.3
• do not affect the V flag.
34.2.5.6.5 Example
MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10, flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags
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