NXP Semiconductors LPC1768 - MII Mgmt Command Register; 0 X5000 0024); MII Mgmt Address Register; 0 X5000 0028)

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User manual Rev. 3 — 19 December 2013 156 of 841
NXP Semiconductors
UM10360
Chapter 10: LPC176x/5x Ethernet
[1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device.
10.11.10 MII Mgmt Command Register (MCMD - 0x5000 0024)
The MII Mgmt Command register (MCMD) has an address of 0x5000 0024. The bit
definition of this register is shown in Table 140
.
10.11.11 MII Mgmt Address Register (MADR - 0x5000 0028)
The MII Mgmt Address register (MADR) has an address of 0x5000 0028. The bit definition
of this register is shown in Table 141
.
10.11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C)
The MII Mgmt Write Data register (MWTD) is a write-only register with an address of
0x5000 002C. The bit definition of this register is shown in Table 142
.
Host Clock divided by 48 1 0 1 1 120
[1]
Host Clock divided by 52 1 1 0 0 130
[1]
Host Clock divided by 56 1 1 0 1 140
[1]
Host Clock divided by 60 1 1 1 0 150
[1]
Host Clock divided by 64 1 1 1 1 160
[1]
Table 139. Clock select encoding
Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB
clock supported
Table 140. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description
Bit Symbol Function Reset
value
0 READ This bit causes the MII Management hardware to perform a single Read cycle. The Read data is
returned in Register MRDD (MII Mgmt Read Data).
0
1 SCAN This bit causes the MII Management hardware to perform Read cycles continuously. This is
useful for monitoring Link Fail for example.
0
31:2 - Unused 0x0
Table 141. MII Mgmt Address register (MADR - address 0x5000 0028) bit description
Bit Symbol Function Reset
value
4:0 REGISTER
ADDRESS
This field represents the 5-bit Register Address field of Mgmt
cycles. Up to 32 registers can be accessed.
0x0
7:5 - Unused 0x0
12:8 PHY ADDRESS This field represents the 5-bit PHY Address field of Mgmt
cycles. Up to 31 PHYs can be addressed (0 is reserved).
0x0
31:13 - Unused 0x0