UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 603 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.5.20 DMA channel control registers (DMACCxControl - 0x5000 41xC)
The eight read/write DMACCxControl Registers (DMACC0Control to DMACC7Control)
contain DMA channel control information such as the transfer size, burst size, and transfer
width. Each register is programmed directly by software before the DMA channel is
enabled. When the channel is enabled the register is updated by following the linked list
when a complete packet of data has been transferred. Reading the register while the
channel is active does not give useful information. This is because by the time software
has processed the value read, the channel may have advanced. It is intended to be
read-only when a channel has stopped. Table 563
shows the bit assignments of the
DMACCxControl Register.
31.5.20.1 Protection and access information
AHB access information is provided to the source and/or destination peripherals when a
transfer occurs, although on the LPC176x/5x this has no effect. The transfer information is
provided by programming the DMA channel (the Prot bits of the DMACCxControl
Register, and the Lock bit of the DMACCxConfig Register). These bits are programmed
by software, and can be used by peripherals. Three bits of information are provided, and
are used as shown in Table 563
.
Table 562. DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)
Bit Name Function
1:0 - Reserved, and must be written as 0.
31:2 LLI Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
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