UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 478 of 841
NXP Semiconductors
UM10360
Chapter 20: LPC176x/5x I2S
20.5.2 Digital Audio Input register (I2SDAI - 0x400A 8004)
The I2SDAI register controls the operation of the I
2
S receive channel. The function of bits
in DAI are shown in Table 406
.
20.5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008)
The I2STXFIFO register provides access to the transmit FIFO. The function of bits in
I2STXFIFO are shown in Table 407
.
20.5.4 Receive FIFO register (I2SRXFIFO - 0x400A 800C)
The I2SRXFIFO register provides access to the receive FIFO. The function of bits in
I2SRXFIFO are shown in Table 408
.
2 mono When 1, data is of monaural format. When 0, the data is in stereo format. 0
3 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0
4 reset When 1, asynchronously resets the transmit channel and FIFO. 0
5 ws_sel When 0, the interface is in master mode. When 1, the interface is in slave mode. See
Section 20.7
for a summary of useful combinations for this bit with I2STXMODE.
1
14:6 ws_halfperiod Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F
15 mute When 1, the transmit channel sends only zeroes. 1
31:16 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description …continued
Bit Symbol Value Description Reset
Value
Table 406: Digital Audio Input register (I2SDAI - address 0x400A 8004) bit description
Bit Symbol Value Description Reset
Value
1:0 wordwidth Selects the number of bytes in data as follows: 01
00 8-bit data
01 16-bit data
10 Reserved, do not use this setting
11 32-bit data
2 mono When 1, data is of monaural format. When 0, the data is in stereo format. 0
3 stop When 1, disables accesses on FIFOs, places the transmit channel in mute mode. 0
4 reset When 1, asynchronously reset the transmit channel and FIFO. 0
5 ws_sel When 0, the interface is in master mode. When 1, the interface is in slave mode. See
Section 20.7
for a summary of useful combinations for this bit with I2SRXMODE.
1
14:6 ws_halfperiod Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F
31:15 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
Table 407: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description
Bit Symbol Description Reset Value
31:0 I2STXFIFO 8 ï‚´ 32-bit transmit FIFO. Level = 0
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