UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 358 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX
Counter content is interpreted and the Bus Off event is performed in the same way as if it
was forced by a bus error event. That means, that the Reset Mode is entered again, the
TX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status
and Interrupt Register bits are set. Clearing of Reset Mode now will perform the protocol
defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal).
If the Reset Mode is entered again before the end of Bus Off recovery (TXERR>0), Bus
Off keeps active and TXERR is frozen.
16.7.4 CAN Interrupt and Capture Register (CAN1ICR - 0x4004 400C,
CAN2ICR - 0x4004 800C)
Bits in this register indicate information about events on the CAN bus. This register is
read-only.
The Interrupt flags of the Interrupt and Capture Register allow the identification of an
interrupt source. When one or more bits are set, a CAN interrupt will be indicated to the
CPU. After this register is read from the CPU all interrupt bits are reset except of the
Receive Interrupt bit. The Interrupt Register appears to the CPU as a read-only memory.
Bits 1 through 10 clear when they are read.
Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in
CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur.
Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in
CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either
of these bytes is captured, its value will remain the same until it is read, at which time it is
released to capture a new value.
The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read
from CANxICR, regardless of whether part or all of the register is read. This means that
software should always read CANxICR as a word, and process and deal with all bits of the
register as appropriate for the application.
Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
bit description
Bit Symbol Value Function Reset
Value
RM
Set
0RI
[1]
0 (reset)
1 (set)
Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE
bit in CANxIER are both 1, indicating that a new message was received and
stored in the Receive Buffer.
00
1 TI1 0 (reset)
1 (set)
Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to
1 (whenever a message out of TXB1 was successfully transmitted or aborted),
indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.
00
2EI 0 (reset)
1 (set)
Error Warning Interrupt. This bit is set on every change (set or clear) of either the
Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the
Interrupt Enable Register at the time of the change.
0X
3 DOI 0 (reset)
1 (set)
Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0
to 1 and the DOIE bit in CANxIER is 1.
00
4WUI
[2]
0 (reset)
1 (set)
Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity
is detected and the WUIE bit in CANxIER is 1.
00
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