NXP Semiconductors LPC1768 - USB Realize Endpoint Register; 0 X5000 C244)

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User manual Rev. 3 — 19 December 2013 232 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.10.4.2 USB Realize Endpoint register (USBReEp - 0x5000 C244)
Writing one to a bit in this register causes the corresponding endpoint to be realized.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.
On reset, only the control endpoints are realized. Other endpoints, if required, are realized
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see Section 11.10.4.1
.
Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is
shown below.
Clear EP_RLZED bit in USBDevIntSt;
for every endpoint to be realized,
{
/* OR with the existing value of the Realize Endpoint register */
USBReEp |= (UInt32) ((0x1 << endpt));
/* Load Endpoint index Reg with physical endpoint no.*/
USBEpIn = (UInt32) endpointnumber;
/* load the max packet size Register */
USBEpMaxPSize = MPS;
/* check whether the EP_RLZED bit in the Device Interrupt Status register is set
*/
while (!(USBDevIntSt & EP_RLZED))
{
/* wait until endpoint realization is complete */
Table 211. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit allocation
Reset value: 0x0000 0003
Bit 31 30 29 28 27 26 25 24
Symbol
EP31 EP30 EP29 EP28 EP27 EP26 EP25 EP24
Bit 23 22 21 20 19 18 17 16
Symbol
EP23 EP22 EP21 EP20 EP19 EP18 EP17 EP16
Bit 15 14 13 12 11 10 9 8
Symbol
EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Bit 7 6 5 4 3 2 1 0
Symbol
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
Table 212. USB Realize Endpoint register (USBReEp - address 0x5000 C244) bit description
Bit Symbol Value Description Reset value
0 EP0 0 Control endpoint EP0 is not realized. 1
1 Control endpoint EP0 is realized.
1 EP1 0 Control endpoint EP1 is not realized. 1
1 Control endpoint EP1 is realized.
31:2 EPxx 0 Endpoint EPxx is not realized. 0
1 Endpoint EPxx is realized.