UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 492 of 841
NXP Semiconductors
UM10360
Chapter 21: LPC176x/5x Timer 0/1/2/3
21.3 Applications
• Interval Timer for counting internal events.
• Pulse Width Demodulator via Capture inputs.
• Free running timer.
21.4 Description
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actions
at specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
21.5 Pin description
Table 424 gives a brief summary of each of the Timer/Counter related pins.
21.5.1 Multiple CAP and MAT pins
Software can select from multiple pins for the CAP or MAT functions in the Pin Select
registers, which are described in Section 8.5
. When more than one pin is selected for a
MAT output, all such pins are driven identically. When more than one pin is selected for a
CAP input, the pin with the lowest Port number is used. Note that match conditions may
be used internally without the use of a device pin.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case cannot be shorter than 1/(2 x PCLK).
Table 424. Timer/Counter pin description
Pin Type Description
CAP0[1:0]
CAP1[1:0]
CAP2[1:0]
CAP3[1:0]
Input Capture Signals- A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt. Capture functionality can be
selected from a number of pins. When more than one pin is selected for a Capture input on a single
TIMER0/1 channel, the pin with the lowest Port number is used
Timer/Counter block can select a capture signal as a clock source instead of the PCLK derived clock.
For more details see Section 21.6.3
.
MAT0[1:0]
MAT1[1:0]
MAT2[3:0]
MAT3[1:0]
Output External Match Output - When a match register (MR3:0) equals the timer counter (TC) this output can
either toggle, go low, go high, or do nothing. The External Match Register (EMR) controls the
functionality of this output. Match Output functionality can be selected on a number of pins in parallel.
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