UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 411 of 841
NXP Semiconductors
UM10360
Chapter 17: LPC176x/5x SPI
17.7.7 SPI Interrupt Register (S0SPINT - 0x4002 001C)
This register contains the interrupt flag for the SPI0 interface.
6 WCOL Write collision. 0
7 SPIF SPI transfer complete flag. 0
31:8 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 366: SPI Test Status Register (SPTSR - address 0x4002 0014) bit description
Bit Symbol Description Reset
Value
Table 367: SPI Interrupt Register (S0SPINT - address 0x4002 001C) bit description
Bit Symbol Description Reset
Value
0 SPIF SPI interrupt flag. Set by the SPI interface to generate an interrupt.
Cleared by writing a 1 to this bit.
Note: this bit will be set once when SPIE = 1 and at least one of SPIF
and WCOL bits is 1. However, only when the SPI Interrupt bit is set and
SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be
processed by interrupt handling software.
0
7:1 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
31:8 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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