UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 326 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated
when the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time and
currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or
a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
15.4.6 UART1 FIFO Control Register (U1FCR - 0x4001 0008)
The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs.
15.4.6.1 DMA Operation
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an
affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.
Table 297: UART1 FIFO Control Register (U1FCR - address 0x4001 0008) bit description
Bit Symbol Value Description Reset Value
0 FIFO Enable 0 UART1 FIFOs are disabled. Must not be used in the application. 0
1 Active high enable for both UART1 Rx and TX FIFOs and U1FCR[7:1] access.
This bit must be set for proper UART1 operation. Any transition on this bit will
automatically clear the UART1 FIFOs.
1RX FIFO
Reset
0 No impact on either of UART1 FIFOs. 0
1 Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx FIFO, reset the
pointer logic. This bit is self-clearing.
2 TX FIFO
Reset
0 No impact on either of UART1 FIFOs. 0
1 Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX FIFO, reset the
pointer logic. This bit is self-clearing.
3 DMA Mode
Select
When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA
mode. See Section 15.4.6.1
.
0
5:4 - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
7:6 RX Trigger
Level
These two bits determine how many receiver UART1 FIFO characters must be
written before an interrupt is activated.
0
00 Trigger level 0 (1 character or 0x01).
01 Trigger level 1 (4 characters or 0x04).
10 Trigger level 2 (8 characters or 0x08).
11 Trigger level 3 (14 characters or 0x0E).
31:8 - Reserved, user software should not write ones to reserved bits. NA
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