UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 445 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
19.8.5 I
2
C Monitor mode control register (I2MMCTRL: I
2
C0, I2C0MMCTRL -
0x4001 C01C; I
2
C1, I2C1MMCTRL- 0x4005 C01C; I
2
C2, I2C2MMCTRL-
0x400A 001C)
This register controls the Monitor mode which allows the I
2
C module to monitor traffic on
the I
2
C-bus without actually participating in traffic or interfering with the I
2
C-bus.
Table 387. I
2
C Data register (I2DAT: I
2
C0, I2C0DAT - 0x4001 C008; I
2
C1, I2C1DAT -
0x4005 C008; I
2
C2, I2C2DAT - 0x400A 0008) bit description
Bit Symbol Description Reset
value
7:0 Data This register holds data values that have been received or are to be
transmitted.
0
31:8 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 388. I
2
C Monitor mode control register (I2MMCTRL: I
2
C0, I2C0MMCTRL - 0x4001 C01C;
I
2
C1, I2C1MMCTRL- 0x4005 C01C; I
2
C2, I2C2MMCTRL- 0x400A 001C) bit
description
Bit Symbol Value Description Reset
value
0 MM_ENA Monitor mode enable. 0
0 Monitor mode disabled.
1 The
I
2
C module will enter monitor mode. In this mode the
SDA output will be put in high impedance mode. This
prevents the
I
2
C module from outputting data of any kind
(including ACK) onto the
I
2
C data bus.
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the
I
2
C clock line.
1 ENA_SCL SCL output enable. 0
0 When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the
I
2
C clock line.
1 When this bit is set, the
I
2
C module may exercise the same
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the
I
2
C
module can “stretch” the clock line (hold it low) until it has
had time to respond to an
I
2
C interrupt.
[1]
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