NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 571 of 841
NXP Semiconductors
UM10360
Chapter 28: LPC176x/5x Watchdog Timer (WDT)
28.3 Description
The Watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (T
WDCLK
 256  4)
and the maximum Watchdog interval is (T
WDCLK
 2
32
 4) in multiples of (T
WDCLK
 4).
The Watchdog should be used in the following manner:
• Set the Watchdog timer constant reload value in WDTC register.
• Setup the Watchdog timer operating mode in WDMOD register.
• Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
• The Watchdog should be fed again before the Watchdog counter underflows to
prevent reset/interrupt.
When the Watchdog is in the reset mode and the counter underflows, the CPU will be
reset, loading the stack pointer and program counter from the vector table as in the case
of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if
the Watchdog has caused the reset condition. The WDTOF flag must be cleared by
software.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
28.4 Register description
The Watchdog contains 4 registers as shown in Table 522 below.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 522. Watchdog register map
Name Description Access Reset
Value
[1]
Address
WDMOD Watchdog mode register. This register contains the basic mode and
status of the Watchdog Timer.
R/W 0 0x4000 0000
WDTC Watchdog timer constant register. This register determines the time-out
value.
R/W 0xFF 0x4000 0004
WDFEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this
register reloads the Watchdog timer with the value contained in WDTC.
WO NA 0x4000 0008
WDTV Watchdog timer value register. This register reads out the current value of
the Watchdog timer.
RO 0xFF 0x4000 000C
WDCLKSEL Watchdog clock source selection register. R/W 0 0x4000 0010

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English