NXP Semiconductors LPC1768 - Interrupt in Monitor Mode; Loss of Arbitration in Monitor Mode

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User manual Rev. 3 — 19 December 2013 446 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
[1] When the ENA_SCL bit is cleared and the I
2
C no longer has the ability to stretch the clock, interrupt
response time becomes important. To give the part more time to respond to an I
2
C interrupt under these
conditions, an I2DATA_BUFFER register is used (Section 19.8.6
) to hold received data for a full 9-bit word
transmission time.
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
19.8.5.1 Interrupt in Monitor mode
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module believes it
has transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
19.8.5.2 Loss of arbitration in Monitor mode
In monitor mode, the I
2
C module will not be able to respond to a request for information by
the bus master or issue an ACK. Some other slave on the bus will respond instead.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected.
2 MATCH_ALL Select interrupt register match. 0
0 When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers, I2ADR0 through I2ADR3. That is, the module will
respond as a normal slave as far as address-recognition is
concerned.
1 When this bit is set to ‘1’ and the
I
2
C is in monitor mode, an
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
31:3 - Reserved. User software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
Table 388. I
2
C Monitor mode control register (I2MMCTRL: I
2
C0, I2C0MMCTRL - 0x4001 C01C;
I
2
C1, I2C1MMCTRL- 0x4005 C01C; I
2
C2, I2C2MMCTRL- 0x400A 001C) bit
description …continued
Bit Symbol Value Description Reset
value