UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 574 of 841
NXP Semiconductors
UM10360
Chapter 28: LPC176x/5x Watchdog Timer (WDT)
28.5 Block diagram
The block diagram of the Watchdog is shown below in the Figure 132. The
synchronization logic (PCLK - WDCLK) is not shown in the block diagram.
Table 528: Watchdog Timer Clock Source Selection register (WDCLKSEL, address 0x4000 0010) bit description
Bit Symbol Value Description Reset
Value
1:0 WDSEL These bits select the clock source for the Watchdog timer as described below.
Warning: Improper setting of this value may result in incorrect operation of the
Watchdog timer, which could adversely affect system operation. If the WDLOCK bit in
this register is set, the WDSEL bit cannot be modified.
0
0x0 IRC. Selects the Internal RC oscillator (irc_clk) as the Watchdog clock source (default).
0x1 PCLK. Selects the APB peripheral clock (watchdog pclk) as the Watchdog clock
source.
0x2 RTC. Selects the RTC oscillator (rtc_clk) as the Watchdog clock source.
0x3 Reserved, this setting should not be used.
30:2 - - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
31 WDLOCK WDT locking. 0
0 Unlocked. This bit is set to 0 on any reset. It cannot be cleared by software.
1 Locked. Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this
register cannot be modified.
Fig 132. Watchdog block diagram
WDTC
32-BIT DOWN COUNTER
WDINT WDTOF WDRESET WDEN
SHADOW BIT
reset
interrupt
ï‚¸ï€ 4
WDFEED
WDCLKSEL
pclk
RTC oscillator
internal RC oscillator
feed ok
feed error
wdclk
underflow
enable
count
WMOD register
feed sequence
WDTV
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