NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 12 of 841
NXP Semiconductors
UM10360
Chapter 1: LPC176x/5x Introductory information
1.10 Block diagram
Fig 2. LPC1768 block diagram, CPU and buses
Multilayer
AHB Matrix
AHB to
APB bridge
AHB to
APB bridge
JTAG
interface Debug Port
Ethernet PHY
interface
SRAM
16 kB
SRAM
16 kB
EMULATION
TRACE MODULE
ARM Cortex-M3
TEST/DEBUG
INTERFACE
USB
device,
host,
OTG
USB
interface
DMA
controller
Ethernet
10/100
MAC
System
bus
D-code
bus
I-code
bus
DMAC
regs
USB
regs
Ethernet
regs
clock generation,
power control,
and other
system functions
SRAM
32 kB
ROM
8 kB
Flash
512 kB
Flash
Accelerator
RST
Xtalin
Xtalout
X32Kin
X32Kout
APB slave group 1
Note: shaded peripheral blocks
support General Purpose DMA
Capture/compare
timers 2 & 3
I
2
C2
I2S
UARTs 2 & 3
SSP0
External interrupts
DAC
System control
Motor control PWM
Quadrature encoder
APB slave group 0
RTC Power Domain
Real Time Clock
SSP1
UARTs 0 & 1
CAN 1 & 2
I
2
C 0 & 1
SPI0
Capture/compare
timers 0 & 1
Watchdog timer
PWM1
12-bit ADC
Pin connect block
GPIO interrupt control
32 kHz
oscillator
Backup registers
(20 bytes)
Repetitive interrupt
timer
ultra-low power
regulator
Vbat
voltage regulator
clocks
and
controls
internal
power
Vdd
CLK
OUT
HS
GPIO

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English