UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 381 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
information under which address during an ID screening an error in the look-up table was
encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up table
interrupt.
16.14.9 LUT Error Address register (LUTerrAd - 0x4003 C018)
16.14.10 LUT Error register (LUTerr - 0x4003 C01C)
16.14.11 Global FullCANInterrupt Enable register (FCANIE - 0x4003 C020)
A write access to the Global FullCAN Interrupt Enable register is only possible when the
Acceptance Filter is in the off mode.
16.14.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0x4003 C024 and
FCANIC1 - 0x4003 C028)
For detailed description on these two registers, see Section 16.16.2 “FullCAN interrupts”.
Table 348. LUT Error Address register (LUTerrAd - address 0x4003 C018) bit description
Bit Symbol Description Reset Value
1:0 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
10:2 LUTerrAd It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup
Table RAM, at which the Acceptance Filter encountered an error in the content of the
tables.
0
31:11 - Reserved, the value read from a reserved bit is not defined. NA
Table 349. LUT Error register (LUTerr - address 0x4003 C01C) bit description
Bit Symbol Description Reset Value
0 LUTerr This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of
the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This
condition is ORed with the “other CAN” interrupts from the CAN controllers, to produce the
request that is connected to the NVIC.
0
31:1 - Reserved, the value read from a reserved bit is not defined. NA
Table 350. Global FullCAN Enable register (FCANIE - address 0x4003 C020) bit description
Bit Symbol Description Reset Value
0 FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled. 0
31:1 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 351. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0x4003 C024) bit description
Bit Symbol Description Reset Value
0 IntPnd0 FullCan Interrupt Pending bit 0. 0
... IntPndx (0<x<31) FullCan Interrupt Pending bit x. 0
31 IntPnd31 FullCan Interrupt Pending bit 31. 0
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