NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 591 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.4.1.6.3 Error conditions
An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The DMA Controller automatically disables
the DMA stream after the current transfer has completed, and can optionally generate an
error interrupt to the CPU. This error interrupt can be masked.
Big Big 8 16 1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12
34
56
78
1/[15:0]
2/[31:16]
12341234
56785678
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2/[23:16]
3/[15:8]
4/[7:0]
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78
1/[31:0] 12345678
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1/[23:16]
2/[15:8]
2/[7:0]
12
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1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12121212
34343434
56565656
78787878
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1/[23:16]
2/[15:8]
2/[7:0]
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1/[15:0]
2/[31:16]
12341234
56785678
Big Big 16 32 1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
12
34
56
78
1/[31:0] 12345678
Big Big 32 8 1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
12
34
56
78
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
12121212
34343434
56565656
78787878
Big Big 32 16 1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
12
34
56
78
1/[15:0]
2/[31:16]
12341234
56785678
Big Big 32 32 1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
12
34
56
78
1/[31:0] 12345678
Table 542. Endian behavior
…continued
Source
endian
Destination
endian
Source
width
Destination
width
Source
transfer
no/byte lane
Source data Destination
transfer
no/byte lane
Destination data

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English