UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 533 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.4.2 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060)
Writing one(s) to this write-only address sets the corresponding bit(s) in MCCNTCON.
25.7.4.3 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064)
Writing one(s) to this write-only address clears the corresponding bit(s) in MCCNTCON.
25.7.5 MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018,
0x400B 801C, 0x400B 8020)
These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each
value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by
MCCNTCON. The timer/counter counts up from 0 until it reaches the value in its
corresponding MCPER register (or is stopped by writing to MCCON_CLR).
A TC register can be read at any time. In order to write to the TC register, its channel must
be stopped. If not, the write will not take place, no exception is generated.
13 TC2MCI0_FE 1 If MODE2 is 1, counter 2 advances on a falling edge on MCI0. 0
0 A falling edge on MCI0 does not affect counter 2.
14 TC2MCI1_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI1. 0
0 A rising edge on MCI1 does not affect counter 2.
15 TC2MCI1_FE 1 If MODE2 is 1, counter 2 advances on a falling edge on MCI1. 0
0 A falling edge on MCI1 does not affect counter 2.
16 TC2MCI2_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI2. 0
0 A rising edge on MCI2 does not affect counter 2.
17 TC2MCI2_FE 1 If MODE2 is 1, counter 2 advances on a falling edge on MCI2. 0
0 A falling edge on MCI2 does not affect counter 2.
28:18 - - Reserved. -
29 CNTR0 1 Channel 0 is in counter mode. 0
0 Channel 0 is in timer mode.
30 CNTR1 1 Channel 1 is in counter mode. 0
0 Channel 1 is in timer mode.
31 CNTR2 1 Channel 2 is in counter mode. 0
0 Channel 2 is in timer mode.
Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description …continued
Bit Symbol Value Description Reset
Value
Table 470. MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description
Bit Description
31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCCNTCON register. See Table 469.
Table 471. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description
Bit Description
31:0 Writing one(s) to this write-only address clears the corresponding bit(s) in the MCCNTCON register. See
Table 469
.
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