UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 673 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
For
LDMDB
,
LDMEA
,
STMDB
, and
STMFD
the memory addresses used for the accesses are at
4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in
reglist. The accesses happen in order of decreasing register numbers, with the highest
numbered register using the highest memory address and the lowest number register
using the lowest memory address. If the writeback suffix is specified, the value of
Rn - 4 * (n-1) is written back to Rn.
The
PUSH
and
POP
instructions can be expressed in this form. See Section 34.2.4.7 for
details.
34.2.4.6.3 Restrictions
In these instructions:
• Rn must not be PC
• reglist must not contain SP
• in any
STM
instruction, reglist must not contain PC
• in any
LDM
instruction, reglist must not contain PC if it contains LR
• reglist must not contain Rn if you specify the writeback suffix.
When PC is in reglist in an
LDM
instruction:
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch
occurs to this halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
34.2.4.6.4 Condition flags
These instructions do not change the flags.
34.2.4.6.5 Examples
LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM
STMDB R1!,{R3-R6,R11,R12}
34.2.4.6.6 Incorrect examples
STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
LDM R2, {} ; There must be at least one register in the list
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