NXP Semiconductors LPC1768 - Chapter 19: Lpc176 X;5 X I2 C0;1;2; Basic Configuration; Features

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 429 of 841
19.1 Basic configuration
The I
2
C0/1/2 interfaces are configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bit PCI2C0/1/2.
Remark: On reset, all I
2
C interfaces are enabled (PCI2C0/1/2 = 1).
2. Clock: In PCLKSEL0 select PCLK_I2C0; in PCLKSEL1 select PCLK_I2C1 or
PCLK_I2C2 (see Section 4.7.3
).
3. Pins: Select I
2
C0, I
2
C1, or I
2
C2 pins through the PINSEL registers. Select the pin
modes for the port pins with I
2
C1 or I
2
C2 functions through the PINMODE registers
(no pull-up, no pull-down resistors) and the PINMODE_OD registers (open drain)
(See Section 8.5
).
Remark: I
2
C0 pins SDA0 and SCL0 are open-drain outputs and fully I
2
C-bus
compliant (see Table 73
). I
2
C0 can be further configured through the I2CPADCFG
register to support Fast Mode Plus (See Table 99
).
Remark: I
2
C0 is not available in the 80-pin package.
Remark: I
2
C pins that do not use specialized I
2
C pads (as identified in Table 73) can
be configured to an open-drain mode via the relevant IOCON registers, and can be
used with fast mode (400 kHz) and standard mode (100 kHz) I
2
C. These pins do not
include an analog filter to suppress line glitches, but a similar function is performed by
the digital filter in the I
2
C block itself. These pins should be configured as: no pull-up,
no pull-down, open drain mode.
4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
5. Initialization: see Section 19.9.8.1
and Section 19.10.1.
19.2 Features
• Standard I
2
C compliant bus interfaces may be configured as Master, Slave, or
Master/Slave.
• Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
• Programmable clock allows adjustment of I
2
C transfer rates.
• Data transfer is bidirectional between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
• Supports Fast Mode Plus (I
2
C0 only).
• Optional recognition of up to 4 distinct slave addresses.
• Monitor mode allows observing all I
2
C-bus traffic, regardless of slave address, without
affecting the actual I
2
C-bus traffic.
• The I
2
C-bus can be used for test and diagnostic purposes.
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
Rev. 3 — 19 December 2013 User manual