NXP Semiconductors LPC1768 - Slave Mode Operation; Interrupt Generation

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 254 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
7. Enable endpoint interrupts (Slave mode):
– Clear all endpoint interrupts using USBEpIntClr.
– Clear any device interrupts using USBDevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
USBEpIntEn.
– Set the priority of each enabled interrupt using USBEpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,
and possibly EP_FAST).
8. Configure the DMA (DMA mode):
– Disable DMA operation for all endpoints using USBEpDMADis.
– Clear any pending DMA requests using USBDMARClr.
– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and
USBSysErrIntClr.
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH.
– Enable the desired endpoints for DMA operation using USBEpDMAEn.
– Set EOT, DDR, and ERR bits in USBDMAIntEn.
9. Install USB interrupt handler in the NVIC by writing its address to the appropriate
vector table location and enabling the USB interrupt in the NVIC.
10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
command. A bus reset will also cause this to happen.
11. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
command.
The configuration of the endpoints varies depending on the software application. By
default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.
11.14 Slave mode operation
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface.
11.14.1 Interrupt generation
In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated
in response to an endpoint interrupt. Endpoint interrupts are enabled using the
USBEpIntEn register, and are observable in the USBEpIntSt register.
All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.