UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 422 of 841
NXP Semiconductors
UM10360
Chapter 18: LPC176x/5x SSP0/1
18.6 Register description
The register addresses of the SSP controllers addresses are shown in Table 369.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
18.6.1 SSPn Control Register 0 (SSP0CR0 - 0x4008 8000, SSP1CR0 - 0x4003
0000)
This register controls the basic operation of the SSP controller.
Table 369. SSP Register Map
Generic
Name
Description Access Reset
Value
[1]
SSPn Register
Name & Address
CR0 Control Register 0. Selects the
serial clock rate, bus type, and data
size.
R/W 0 SSP0CR0 - 0x4008 8000
SSP1CR0 - 0x4003 0000
CR1 Control Register 1. Selects
master/slave and other modes.
R/W 0 SSP0CR1 - 0x4008 8004
SSP1CR1 - 0x4003 0004
DR Data Register. Writes fill the
transmit FIFO, and reads empty
the receive FIFO.
R/W 0 SSP0DR - 0x4008 8008
SSP1DR - 0x4003 0008
SR Status Register RO SSP0SR - 0x4008 800C
SSP1SR - 0x4003 000C
CPSR Clock Prescale Register R/W 0 SSP0CPSR - 0x4008 8010
SSP1CPSR - 0x4003 0010
IMSC Interrupt Mask Set and Clear
Register
R/W 0 SSP0IMSC - 0x4008 8014
SSP1IMSC - 0x4003 0014
RIS Raw Interrupt Status Register R/W SSP0RIS - 0x4008 8018
SSP1RIS - 0x4003 0018
MIS Masked Interrupt Status Register R/W 0 SSP0MIS - 0x4008 801C
SSP1MIS - 0x4003 001C
ICR SSPICR Interrupt Clear Register R/W NA SSP0ICR - 0x4008 8020
SSP1ICR - 0x4003 0020
DMACR DMA Control Register R/W 0 SSP0DMACR - 0x4008 8024
SSP1DMACR - 0x4003 0024
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