UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 667 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.
34.2.4.3.4 Condition flags
These instructions do not change the flags.
34.2.4.3.5 Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2
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