UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 790 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
• For privileged accesses, the default memory map is as described in Section 34.3.2
“Memory model”. Any access by privileged software that does not address an enabled
memory region behaves as defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory
region causes a memory management fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of
the value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled
for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit
is set to 1 and no regions are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the
same memory attributes as if the MPU is not implemented, see Table 635 “
Memory
access behavior”. The default memory map applies to accesses from both privileged and
unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are
always permitted. Other areas are accessible based on regions and whether
PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing
the handler for an exception with priority –1 or –2. These priorities are only possible when
handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the
HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
34.4.5.3 MPU Region Number Register
The RNR selects which memory region is referenced by the RBAR and RASR registers.
See the register summary in Table 680
for its attributes. The bit assignments are shown in
Table 683
.
Normally, you write the required region number to this register before accessing the
RBAR or RASR. However you can change the region number by writing to the RBAR with
the VALID bit set to 1, see Table 684
. This write updates the value of the REGION field.
34.4.5.4 MPU Region Base Address Register
The RBAR defines the base address of the MPU region selected by the RNR, and can
update the value of the RNR. See the register summary in Table 680
for its attributes.
Write RBAR with the VALID bit set to 1 to change the current region number and update
the RNR. The bit assignments are shown in Table 684
.
Table 683. RNR bit assignments
Bits Name Function
[31:8] - Reserved.
[7:0] REGION Indicates the MPU region referenced by the RBAR and RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field
are 0-7.
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