UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 702 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.8.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
34.2.8.1.1 Syntax
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see Section 34.2.3.7 “
Conditional execution”.
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
width is the width of the bitfield and must be in the range 1 to 32lsb.
34.2.8.1.2 Operation
BFC
clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position
lsb
. Other bits in Rd are unchanged.
BFI
copies a bitfield into one register from another register. It replaces width bits in Rd
starting at the low bit position
lsb
, with width bits from Rn starting at bit[0]. Other bits in Rd
are unchanged.
34.2.8.1.3 Restrictions
Do not use SP and do not use PC.
34.2.8.1.4 Condition flags
These instructions do not affect the flags.
34.2.8.1.5 Examples
BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0
BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2
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