UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 475 of 841
NXP Semiconductors
UM10360
Chapter 20: LPC176x/5x I2S
20.3 Description
The I
2
S performs serial data out via the transmit channel and serial data in via the receive
channel. These support the NXP Inter IC Audio format for 8-bit, 16-bit and 32-bit audio
data, both for stereo and mono modes. Configuration, data access and control is
performed by a APB register set. Data streams are buffered by FIFOs with a depth of
8 words.
The I
2
S receive and transmit stage can operate independently in either slave or master
mode. Within the I
2
S module the difference between these modes lies in the word select
(WS) signal which determines the timing of data transmissions. Data words start on the
next falling edge of the transmitting clock after a WS change. In stereo mode when WS is
low left data is transmitted and right data when WS is high. In mono mode the same data
is transmitted twice, once when WS is low and again when WS is high.
• In master mode, word select is generated internally with a 9-bit counter. The half
period count value of this counter can be set in the control register.
• In slave mode, word select is input from the relevant bus pin.
• When an I
2
S-bus is active, the word select, receive clock and transmit clock signals
are sent continuously by the bus master, while data is sent continuously by the
transmitter.
• Disabling the I
2
S can be done with the stop or mute control bits separately for the
transmit and receive.
• The stop bit will disable accesses by the transmit channel or the receive channel to
the FIFOs and will place the transmit channel in mute mode.
• The mute control bit will place the transmit channel in mute mode. In mute mode, the
transmit channel FIFO operates normally, but the output is discarded and replaced by
zeroes. This bit does not affect the receive channel, data reception can occur
normally.
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