UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 339 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
Although Table 307 describes how to use TxEn bit in order to achieve hardware flow
control, it is strongly suggested to let UART1 hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
U1TER enables implementation of software and hardware flow control. When TXEn=1,
UART1 transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UART1 transmission will stop.
Table 307
describes how to use TXEn bit in order to achieve software flow control.
15.4.18 UART1 RS485 Control register (U1RS485CTRL - 0x4001 004C)
The U1RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 307: UART1 Transmit Enable Register (U1TER - address 0x4001 0030) bit description
Bit Symbol Description Reset Value
6:0 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
7 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as
soon as any preceding data has been sent. If this bit cleared to 0 while a character is being
sent, the transmission of that character is completed, but no further characters are sent until
this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the
THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects
that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software
handshaking, when it receives an XOFF character (DC3). Software can set this bit again
when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1)
character.
1
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description
Bit Symbol Value Description Reset value
0 NMMEN 0 RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0
1 RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an
address is detected when a received byte causes the UART to set the parity error
and generate an interrupt.
1 RXDIS 0 The receiver is enabled. 0
1 The receiver is disabled.
2 AADEN 0 Auto Address Detect (AAD) is disabled. 0
1 Auto Address Detect (AAD) is enabled.
3 SEL 0 If direction control is enabled (bit DCTRL = 1), pin RTS
is used for direction control. 0
1 If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
4 DCTRL 0 Disable Auto Direction Control. 0
1 Enable Auto Direction Control.
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