UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 76 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.4 Vector table remapping
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register (VTOR) contained in the Cortex-M3.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table should be located on a 256 word (1024 byte) boundary to insure
alignment on LPC176x/5x family devices. Refer to Section 34.4.3.5
of the Cortex-M3 User
Guide appended to this manual for details of the Vector Table Offset feature.
ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code
or SRAM. For simplicity, this bit can be thought as simply part of the address offset since
the split between the “code” space and the “SRAM” space occurs at the location
corresponding to bit 29 in a memory address.
Examples:
To place the vector table at the beginning of the “local” static RAM, starting at address
0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address
0x1000 0000 in the code space, since bit 29 of the VTOR equals 0.
To place the vector table at the beginning of the AHB static RAM, starting at address
0x2007 C000, place the value 0x2007 C000 in the VTOR register. This indicates address
0x2007 C000 in the SRAM space, since bit 29 of the VTOR equals 1.
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