UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 443 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
2
C Interrupt Flag. This bit is set when the I
2
C state changes. However, entering
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register. The SI bit
should be cleared only after the required bit(s) has (have) been set and the value in I2DAT
has been loaded or read.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
1. A matching address defined by registers I2ADR0 through I2ADR3, masked by
I2MASK0 though I2MASK3, has been received.
2. The General Call address has been received while the General Call bit (GC) in I2ADR
is set.
3. A data byte has been received while the I
2
C is in the master receiver mode.
4. A data byte has been received while the I
2
C is in the addressed slave receiver mode
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
1. A data byte has been received while the I
2
C is in the master receiver mode.
2. A data byte has been received while the I
2
C is in the addressed slave receiver mode.
19.8.2 I
2
C Control Clear register (I2CONCLR: I
2
C0, I2C0CONCLR -
0x4001 C018; I
2
C1, I2C1CONCLR - 0x4005 C018; I
2
C2, I2C2CONCLR -
0x400A 0018)
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
2
C interface. Writing a one to a bit of this register causes the
corresponding bit in the I
2
C control register to be cleared. Writing a zero has no effect.
I2CONCLR is a write-only register. The value of the related bits can be read from the
I2CONSET register.
Table 385. I
2
C Control Clear register (I2CONCLR: I
2
C0, I2C0CONCLR - 0x4001 C018;
I
2
C1, I2C1CONCLR - 0x4005 C018; I
2
C2, I2C2CONCLR - 0x400A 0018) bit
description
Bit Symbol Description
1:0 - Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
2 AAC Assert acknowledge Clear bit.
3SIC I
2
C interrupt Clear bit.
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