NXP Semiconductors LPC1768 - DMA Enabled Channel Register (Dmacenbldchns - 0 X5000 401 C); DMA Software Burst Request Register (Dmacsoftbreq - 0 X5000 4020)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 598 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.5.8 DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)
The DMACEnbldChns Register is read-only and indicates which DMA channels are
enabled, as indicated by the Enable bit in the DMACCxConfig Register. A 1 bit indicates
that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer.
Table 552
shows the bit assignments of the DMACEnbldChns Register.
31.5.9 DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
The DMACSoftBReq Register is read/write and enables DMA burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Reading the register indicates which sources are requesting DMA burst
transfers. A request can be generated from either a peripheral or the software request
register. Each bit is cleared when the related transaction has completed. Table 553
shows
the bit assignments of the DMACSoftBReq Register.
Note: It is recommended that software and hardware peripheral requests are not used at
the same time.
Table 551. DMA Raw Error Interrupt Status register (DMACRawIntErrStat - 0x5000 4018)
Bit Name Function
7:0 RawIntErrStat Status of the error interrupt for DMA channels prior to masking. Each bit represents
one channel:
0 - the corresponding channel has no active error interrupt request.
1 - the corresponding channel does have an active error interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 552. DMA Enabled Channel register (DMACEnbldChns - 0x5000 401C)
Bit Name Function
7:0 EnabledChannels Enable status for DMA channels. Each bit represents one channel:
0 - DMA channel is disabled.
1 - DMA channel is enabled.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 553. DMA Software Burst Request register (DMACSoftBReq - 0x5000 4020)
Bit Name Function
15:0 SoftBReq Software burst request flags for each of 16 possible sources. Each bit represents one
DMA request line or peripheral function (refer to Table 543
for peripheral hardware
connections to the DMA controller):
0 - writing 0 has no effect.
1 - writing 1 generates a DMA burst request for the corresponding request line.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.