NXP Semiconductors LPC1768 - MCPWM Count Control Register; MCPWM Count Control Read Address (MCCNTCON - 0 X400 B 805 C)

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User manual Rev. 3 — 19 December 2013 532 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.4 MCPWM Count Control register
25.7.4.1 MCPWM Count Control read address (MCCNTCON - 0x400B 805C)
The MCCNTCON register controls whether the MCPWM channels are in timer or counter
mode, and in counter mode whether the counter advances on rising and/or falling edges
on any or all of the three MCI inputs. If timer mode is selected, the counter advances
based on the PCLK clock.
This address is read-only. To set or clear the register bits, write ones to the
MCCNTCON_SET or MCCNTCON_CLR address.
Table 468. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit
description
Bit Description
31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF
register, thus clearing the corresponding interrupt request(s). See Table 462
.
Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description
Bit Symbol Value Description Reset
Value
0 TC0MCI0_RE 1 If MODE0 is 1, counter 0 advances on a rising edge on MCI0. 0
0 A rising edge on MCI0 does not affect counter 0.
1 TC0MCI0_FE 1 If MODE0 is 1, counter 0 advances on a falling edge on MCI0. 0
0 A falling edge on MCI0 does not affect counter 0.
2 TC0MCI1_RE 1 If MODE0 is 1, counter 0 advances on a rising edge on MCI1. 0
0 A rising edge on MCI1 does not affect counter 0.
3 TC0MCI1_FE 1 If MODE0 is 1, counter 0 advances on a falling edge on MCI1. 0
0 A falling edge on MCI1 does not affect counter 0.
4 TC0MCI2_RE 1 If MODE0 is 1, counter 0 advances on a rising edge on MCI2. 0
0 A rising edge on MCI0 does not affect counter 0.
5 TC0MCI2_FE 1 If MODE0 is 1, counter 0 advances on a falling edge on MCI2. 0
0 A falling edge on MCI0 does not affect counter 0.
6 TC1MCI0_RE 1 If MODE1 is 1, counter 1 advances on a rising edge on MCI0. 0
0 A rising edge on MCI0 does not affect counter 1.
7 TC1MCI0_FE 1 If MODE1 is 1, counter 1 advances on a falling edge on MCI0. 0
0 A falling edge on MCI0 does not affect counter 1.
8 TC1MCI1_RE 1 If MODE1 is 1, counter 1 advances on a rising edge on MCI1. 0
0 A rising edge on MCI1 does not affect counter 1.
9 TC1MCI1_FE 1 If MODE1 is 1, counter 1 advances on a falling edge on MCI1. 0
0 A falling edge on MCI0 does not affect counter 1.
10 TC1MCI2_RE 1 If MODE1 is 1, counter 1 advances on a rising edge on MCI2. 0
0 A rising edge on MCI2 does not affect counter 1.
11 TC1MCI2_FE 1 If MODE1 is 1, counter 1 advances on a falling edge on MCI2. 0
0 A falling edge on MCI2 does not affect counter 1.
12 TC2MCI0_RE 1 If MODE2 is 1, counter 2 advances on a rising edge on MCI0. 0
0 A rising edge on MCI0 does not affect counter 2.