NXP Semiconductors LPC1768 - Interrupt Priority Register 6 (IPR6 - 0 Xe000 E418); Interrupt Priority Register 7 (IPR7 - 0 Xe000 E41 C); Interrupt Priority Register 8 (IPR8 - 0 Xe000 E420)

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User manual Rev. 3 — 19 December 2013 90 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418)
The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
6.5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)
The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
6.5.19 Interrupt Priority Register 8 (IPR8 - 0xE000 E420)
The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts.
Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_USB USB Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_CAN CAN Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_DMA GPDMA Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_I2S I
2
S Interrupt Priority. See functional description for bits 7-3.
Table 69. Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_ENET Ethernet Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_RIT Repetitive Interrupt Timer Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_MCPWM Motor Control PWM Interrupt Priority. See functional description for bits 7-3.
26:24 Unimplemented These bits ignore writes, and read as 0.
31:27 IP_QEI Quadrature Encoder Interface Interrupt Priority. See functional description for bits 7-3.
Table 70. Interrupt Priority Register 8 (IPR8 - 0xE000 E420)
Bit Name Function
2:0 Unimplemented These bits ignore writes, and read as 0.
7:3 IP_PLL1 PLL1 (USB PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8 Unimplemented These bits ignore writes, and read as 0.
15:11 IP_USBACT USB Activity Interrupt Priority. See functional description for bits 7-3.
18:16 Unimplemented These bits ignore writes, and read as 0.
23:19 IP_CANACT CAN Activity Interrupt Priority. See functional description for bits 7-3.
31:24 Unimplemented These bits ignore writes, and read as 0.