UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 679 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
34.2.5.1.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
op is one of:
ADD:
Add.
ADC:
Add with Carry.
SUB:
Subtract.
RSB:
Reverse Subtract.
S: is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see Section 34.2.3.7 “
Conditional execution”.
cond: is an optional condition code, see Section 34.2.3.7 “
Conditional execution”.
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See Section 34.2.3.3
for details of the options.
imm12 is any value in the range 0-4095.
34.2.5.1.2 Operation
The
ADD
instruction adds the value of Operand2 or imm12 to the value in Rn.
The
ADC
instruction adds the values in Rn and Operand2, together with the carry flag.
The
SUB
instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The
SBC
instruction subtracts the value of Operand2 from the value in Rn. If the carry flag
is clear, the result is reduced by one.
The
RSB
instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use
ADC
and
SBC
to synthesize multiword arithmetic, see Section 34.2.5.1.6.
See also Section 34.2.4.1
.
Remark:
ADDW
is equivalent to the
ADD
syntax that uses the imm12 operand.
SUBW
is
equivalent to the
SUB
syntax that uses the imm12 operand.
34.2.5.1.3 Restrictions
• Operand2 must not be SP and must not be PC
• Rd can be SP only in
ADD
and
SUB
, and only with the additional restrictions:
To Next Page
Loading...
