NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 240 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.10.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294)
Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to
generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn
is a read/write register.
11.10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0)
When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read-only register.
Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description
Bit Symbol Value Description Reset value
0 EOT End of Transfer Interrupt bit. 0
0 All bits in the USBEoTIntSt register are 0.
1 At least one bit in the USBEoTIntSt is set.
1 NDDR New DD Request Interrupt bit. 0
0 All bits in the USBNDDRIntSt register are 0.
1 At least one bit in the USBNDDRIntSt is set.
2 ERR System Error Interrupt bit. 0
0 All bits in the USBSysErrIntSt register are 0.
1 At least one bit in the USBSysErrIntSt is set.
31:3 - - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
Table 231. USB DMA Interrupt Enable register (USBDMAIntEn - address 0x5000 C294) bit description
Bit Symbol Value Description Reset value
0 EOT End of Transfer Interrupt enable bit. 0
0 The End of Transfer Interrupt is disabled.
1 The End of Transfer Interrupt is enabled.
1 NDDR New DD Request Interrupt enable bit. 0
0 The New DD Request Interrupt is disabled.
1 The New DD Request Interrupt is enabled.
2 ERR System Error Interrupt enable bit. 0
0 The System Error Interrupt is disabled.
1 The System Error Interrupt is enabled.
31:3 - - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
Table 232. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description
Bit Symbol Value Description Reset value
31:0 EPxx Endpoint xx (2 xx 31) End of Transfer Interrupt request. 0
0 There is no End of Transfer interrupt request for endpoint xx.
1 There is an End of Transfer Interrupt request for endpoint xx.

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English