UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 430 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
• I
2
C0 is a standard I
2
C compliant bus interface with open-drain pins. This interface
supports functions described in the I
2
C specification for speeds up to 1 MHz (Fast
Mode Plus). This includes multi-master operation and allows powering off this device
in a working system while leaving the I
2
C-bus functional.
19.3 Applications
Interfaces to external I
2
C standard parts, such as serial RAMs, LCDs, tone generators,
other microcontrollers, etc.
19.4 Description
A typical I
2
C-bus configuration is shown in Figure 84. Depending on the state of the
direction bit (R/W), two types of data transfers are possible on the I
2
C-bus:
• Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte, unless the slave device is unable
to accept more data.
• Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I
2
C-bus will not be
released.
The LPC176x/5x I
2
C interfaces are byte oriented and have four operating modes: master
transmitter mode, master receiver mode, slave transmitter mode and slave receiver
mode.
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