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User manual Rev. 3 — 20 December 2013 784 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.4.4 System timer, SysTick
The processor has a 24-bit system timer, SysTick, that counts down from the reload value
to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then
counts down on subsequent clocks.
Note: refer to the separate chapter in the LPC176x/5x User Manual Section 23.1
for
device specific information on the System Timer.
Remark: when the processor is halted for debugging the counter does not decrement.
The system timer registers are:
[1] SysTick calibration value. This value is specific to LPC176x/5x devices.
34.4.4.1 SysTick Control and Status Register
The SysTick CTRL register enables the SysTick features. See the register summary in
Table 674
for its attributes. The bit assignments are shown in Table 675.
When ENABLE is set to 1, the counter loads the RELOAD value from the LOAD register
and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts
the SysTick depending on the value of TICKINT. It then loads the RELOAD value again,
and begins counting.
Table 674. System timer registers summary
Address Name Type Required
privilege
Reset
value
Description
0xE000E010
CTRL RW Privileged
0x00000004
Table 675
0xE000E014
LOAD RW Privileged
0x00000000
Table 676
0xE000E018
VAL RW Privileged
0x00000000
Table 677
0xE000E01C
CALIB RO Privileged
0x000F423F
[1]
Table 678
Table 675. SysTick CTRL register bit assignments
Bits Name Function
[31:17] - Reserved.
[16] COUNTFLAG Returns 1 if timer counted to 0 since last time this was read.
[15:3] - Reserved.
[2] CLKSOURCE Indicates the clock source:
0 = external clock
1 = processor clock.
[1] TICKINT Enables SysTick exception request:
0 = counting down to zero does not assert the SysTick exception
request
1 = counting down to zero to asserts the SysTick exception request.
Software can use COUNTFLAG to determine if SysTick has ever
counted to zero.
[0] ENABLE Enables the counter:
0 = counter disabled
1 = counter enabled.