UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 612 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.6.3.1 Hardware interrupt sequence flow
When a DMA interrupt request occurs, the Interrupt Service Routine needs to:
1. Read the DMACIntTCStat Register to determine whether the interrupt was generated
due to the end of the transfer (terminal count). A 1 bit indicates that the transfer
completed. If more than one request is active, it is recommended that the highest
priority channels be checked first.
2. Read the DMACIntErrStat Register to determine whether the interrupt was generated
due to an error occurring. A 1 bit indicates that an error occurred.
3. Service the interrupt request.
4. For a terminal count interrupt, write a 1 to the relevant bit of the DMACIntTCClr
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
31.6.4 Address generation
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported).
Some devices, especially memories, disallow burst accesses across certain address
boundaries. The DMA controller assumes that this is the case with any source or
destination area, which is configured for incrementing addressing. This boundary is
assumed to be aligned with the specified burst size. For example, if the channel is set for
16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is
address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then,
instead of a burst, that transfer is split into separate AHB transactions.
31.6.4.1 Word-aligned transfers across a boundary
The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a
destination for which address incrementing is enabled. The start address for the current
burst is 0x0C000024, the next boundary (calculated from the burst size and transfer
width) is 0x0C000040.
The transfer will be split into two AHB transactions:
• a 7-transfer burst starting at address 0x0C000024
• a 9-transfer burst starting at address 0x0C000040.
31.6.5 Scatter/gather
Scatter/gather is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required, the DMACCxLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the DMA Controller.
The data to be transferred described by an LLI (referred to as the packet of data) usually
requires one or more DMA bursts (to each of the source and destination).
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