UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 463 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
19.9.6 Miscellaneous states
There are two I2STAT codes that do not correspond to a defined I
2
C hardware state (see
Table 402
). These are discussed below.
19.9.6.1 I2STAT = 0xF8
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I
2
C block
is not involved in a serial transfer.
19.9.6.2 I2STAT = 0x00
This status code indicates that a bus error has occurred during an I
2
C serial transfer. A
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I
2
C block signals. When a bus error occurs, SI is
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This
causes the I
2
C block to enter the “not addressed” slave mode (a defined state) and to
clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
19.9.7 Some special cases
The I
2
C hardware has facilities to handle the following special cases that may occur
during a serial transfer:
19.9.7.1 Simultaneous repeated START conditions from two masters
A repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
repeated START condition (see Figure 97
). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
Table 402. Miscellaneous States
Status
Code
(I2CSTAT)
Status of the I
2
C-bus
and hardware
Application software response Next action taken by I
2
C hardware
To/From I2DAT To I2CON
STA STO SI AA
0xF8 No relevant state
information available;
SI = 0.
No I2DAT action No I2CON action Wait or proceed current transfer.
0x00 Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
2
C block
to enter an undefined
state.
No I2DAT action 0 1 0 X Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
2
C
block is switched to the not addressed
SLV mode. STO is reset.
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