UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 355 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
[1] - Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed in
case of an error or arbitration lost (single shot transmission).
- Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature.
No re-transmission will be performed in case of an error or arbitration lost.
- Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The
moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically.
- Setting TR and SRR simultaneously will ignore the set SRR bit.
[2] If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the
bits. The requested transmission may only be cancelled by setting the Abort Transmission bit.
[3] The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a
more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either
transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit
Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated.
[4] After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'.
This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is
reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated.
[5] This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun
Status bit is set no further Data Overrun Interrupt is generated.
[6] Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding
identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 16.7.1 “
CAN Mode
register (CAN1MOD - 0x4004 4000, CAN2MOD - 0x4004 8000)”).
16.7.3 CAN Global Status Register (CAN1GSR - 0x4004 x008, CAN2GSR -
0x4004 8008)
The content of the Global Status Register reflects the status of the CAN Controller. This
register is read-only, except that the Error Counters can be written when the RM bit in the
CANMOD register is 1. Bits not listed read as 0 and should be written as 0.
5 STB1 Select Tx Buffer 1. 0 0
0 (not selected) Tx Buffer 1 is not selected for transmission.
1 (selected) Tx Buffer 1 is selected for transmission.
6 STB2 Select Tx Buffer 2. 0 0
0 (not selected) Tx Buffer 2 is not selected for transmission.
1 (selected) Tx Buffer 2 is selected for transmission.
7 STB3 Select Tx Buffer 3. 0 0
0 (not selected) Tx Buffer 3 is not selected for transmission.
1 (selected) Tx Buffer 3 is selected for transmission.
31:8 - Reserved, user software should not write ones to reserved bits. NA
Table 318. CAN Command Register (CAN1CMR - address 0x4004 4004, CAN2CMR - address 0x4004 8004) bit
description
Bit Symbol Value Function Reset
Value
RM
Set
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