NXP Semiconductors LPC1768 - Fast GPIO Port Mask Register Fioxmask (FIO0 MASK to FIO4 MASK - 0 X2009 C010 to 0 X2009 C090)

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User manual Rev. 3 — 19 December 2013 130 of 841
NXP Semiconductors
UM10360
Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO)
9.5.5 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK -
0x2009 C010 to 0x2009 C090)
This register is used to select port pins that will and will not be affected by write accesses
to the FIOxPIN, FIOxSET or FIOxCLR register. Mask register also filters out port’s content
when the FIOxPIN register is read.
A zero in this register’s bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, corresponding pin will not be changed with
write access and if read, will not be reflected in the updated FIOxPIN register. For
software examples, see Section 9.6
.
FIOxPIN3 Fast GPIO Port x Pin value
register 3. Bit 0 in FIOxPIN3
register corresponds to pin
Px.24 … bit 7 to pin Px.31.
8 (byte)
R/W
0x00 FIO0PIN3 - 0x2009 C017
FIO1PIN3 - 0x2009 C037
FIO2PIN3 - 0x2009 C057
FIO3PIN3 - 0x2009 C077
FIO4PIN3 - 0x2009 C097
FIOxPINL Fast GPIO Port x Pin value
Lower half-word register. Bit 0
in FIOxPINL register
corresponds to pin Px.0 … bit
15 to pin Px.15.
16 (half-word)
R/W
0x0000 FIO0PINL - 0x2009 C014
FIO1PINL - 0x2009 C034
FIO2PINL - 0x2009 C054
FIO3PINL - 0x2009 C074
FIO4PINL - 0x2009 C094
FIOxPINU Fast GPIO Port x Pin value
Upper half-word register. Bit 0
in FIOxPINU register
corresponds to pin Px.16 … bit
15 to Px.31.
16 (half-word)
R/W
0x0000 FIO0PINU - 0x2009 C016
FIO1PINU - 0x2009 C036
FIO2PINU - 0x2009 C056
FIO3PINU - 0x2009 C076
FIO4PINU - 0x2009 C096
Table 110. Fast GPIO port Pin value byte and half-word accessible register
description …continued
Generic
Register
name
Description Register
length (bits)
& access
Reset
value
PORTn Register
Address & Name
Table 111. Fast GPIO port Mask register (FIO0MASK to FIO4MASK - addresses 0x2009 C010
to 0x2009 C090) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0MASK
FIO1MASK
FIO2MASK
FIO3MASK
FIO4MASK
Fast GPIO physical pin access control. 0x0
0 Controlled pin is affected by writes to the port’s FIOxSET,
FIOxCLR, and FIOxPIN register(s). Current state of the pin
can be read from the FIOxPIN register.
1 Controlled pin is not affected by writes into the port’s
FIOxSET, FIOxCLR and FIOxPIN register(s). When the
FIOxPIN register is read, this bit will not be updated with the
state of the physical pin.