UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 493 of 841
NXP Semiconductors
UM10360
Chapter 21: LPC176x/5x Timer 0/1/2/3
21.6 Register description
Each Timer/Counter contains the registers shown in Table 425 ("Reset Value" refers to the
data stored in used bits only; it does not include reserved bits content). More detailed
descriptions follow.
Table 425. TIMER/COUNTER0-3 register map
Generic
Name
Description Access Reset
Value
[1]
TIMERn Register/
Name & Address
IR Interrupt Register. The IR can be written to clear interrupts. The IR
can be read to identify which of eight possible interrupt sources are
pending.
R/W 0 T0IR - 0x4000 4000
T1IR - 0x4000 8000
T2IR - 0x4009 0000
T3IR - 0x4009 4000
TCR Timer Control Register. The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset
through the TCR.
R/W 0 T0TCR - 0x4000 4004
T1TCR - 0x4000 8004
T2TCR - 0x4009 0004
T3TCR - 0x4009 4004
TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
R/W 0 T0TC - 0x4000 4008
T1TC - 0x4000 8008
T2TC - 0x4009 0008
T3TC - 0x4009 4008
PR Prescale Register. When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
R/W 0 T0PR - 0x4000 400C
T1PR - 0x4000 800C
T2PR - 0x4009 000C
T3PR - 0x4009 400C
PC Prescale Counter. The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC
is incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
R/W 0 T0PC - 0x4000 4010
T1PC - 0x4000 8010
T2PC - 0x4009 0010
T3PC - 0x4009 4010
MCR Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
R/W 0 T0MCR - 0x4000 4014
T1MCR - 0x4000 8014
T2MCR - 0x4009 0014
T3MCR - 0x4009 4014
MR0 Match Register 0. MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt
every time MR0 matches the TC.
R/W 0 T0MR0 - 0x4000 4018
T1MR0 - 0x4000 8018
T2MR0 - 0x4009 0018
T3MR0 - 0x4009 4018
MR1 Match Register 1. See MR0 description. R/W 0 T0MR1 - 0x4000 401C
T1MR1 - 0x4000 801C
T2MR1 - 0x4009 001C
T3MR1 - 0x4009 401C
MR2 Match Register 2. See MR0 description. R/W 0 T0MR2 - 0x4000 4020
T1MR2 - 0x4000 8020
T2MR2 - 0x4009 0020
T3MR2 - 0x4009 4020
MR3 Match Register 3. See MR0 description. R/W 0 T0MR3 - 0x4000 4024
T1MR3 - 0x4000 8024
T2MR3 - 0x4009 0024
T3MR3 - 0x4009 4024
CCR Capture Control Register. The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether
or not an interrupt is generated when a capture takes place.
R/W 0 T0CCR - 0x4000 4028
T1CCR - 0x4000 8028
T2CCR - 0x4009 0028
T3CCR - 0x4009 4028
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