UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 645 of 841
NXP Semiconductors
UM10360
Chapter 33: LPC176x/5x JTAG, Serial Wire Debug (SWD), and Trace
Another issue is that debug mode changes the way in which reduced power modes are
handled by the Cortex-M3 CPU. This causes power modes at the device level to be
different from normal modes operation. These differences mean that power
measurements should not be made while debugging, the results will be higher than during
normal operation in an application.
During a debugging session, the System Tick Timer and the Repetitive Interrupt Timers
are automatically stopped whenever the CPU is stopped. Other peripherals are not
affected. If the Repetitive Interrupt Timer is configured such that its PCLK rate is lower
than the CPU clock rate, the RIT may not increment predictably during some debug
operations, such as single stepping.
Debugging is disabled if code read protection is enabled.
The bootloader uses the SRAM during execution. When a system reset is issued to the
core and peripherals during a debug session, SRAM 0x10000120 will be used by the
bootloader.The boot code uses a complete word (“0x10000120…0x10000123” or “32-bit
SRAM word 0x10000120”).
33.6 Debug memory re-mapping
Following chip reset, a portion of the Boot ROM is mapped to address 0 so that it will be
automatically executed. The Boot ROM switches the map to point to Flash memory prior
to user code being executed. In this way a user normally does not need to know that this
re-mapping occurs.
However, when a debugger halts CPU execution immediately following reset, the Boot
ROM is still mapped to address 0 and can cause confusion. Ideally, the debugger should
correct the mapping automatically in this case, so that a user does not need to deal with it.
33.6.1 Memory Mapping Control register (MEMMAP - 0x400F C040)
The MEMMAP register allows switch the mapping of the bottom of memory, including
default reset and interrupt vectors, between the Boot ROM and the bottom of on-chip
Flash memory.
33.7 JTAG TAP Identification
The JTAG TAP controller contains device ID that can be used by debugging software to
identify the general type of device. More detailed device information is available through
ISP/IAP commands (see Section 32.7
and Section 32.8). For the LPC176x/5x family, this
ID value is 0x4BA0 0477.
Table 611. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
Bit Symbol Value Description Reset
value
0 MAP Memory map control. 0
0 Boot mode. A portion of the Boot ROM is mapped to address 0.
1 User mode. The on-chip Flash memory is mapped to address 0.
31:1 - Reserved. The value read from a reserved bit is not defined. NA
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