NXP Semiconductors LPC1768 - Chapter 20: Lpc176 X;5 X I2 S; Basic Configuration; Features

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 474 of 841
20.1 Basic configuration
The I
2
S interface is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bit PCI2S.
Remark: On reset, the I
2
S interface is disabled (PCI2S = 0).
2. Clock: In PCLKSEL1 select PCLK_I2S, see Table 41
.
3. Pins: Select I
2
S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
PINMODE4 (see Section 8.5
).
4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
5. DMA: The I
2
S interface supports two DMA requests, see Table 410 and Table 411,
and Table 543
.
20.2 Features
The I
2
S-bus provides a standard communication interface for digital audio applications.
The I
2
S-bus specification defines a 3-wire serial bus, having one data, one clock, and one
word select signal. The basic I
2
S connection has one master, which is always the master,
and one slave. The I
2
S interface on the LPC176x/5x provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
• The I
2
S input can operate in both master and slave mode.
The I
2
S output can operate in both master and slave mode, independent of the I
2
S
input.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.
• The sampling frequency (fs) can range (in practice) from 16 to 96 kHz. (16, 22.05, 32,
44.1, 48, or 96 kHz) for audio applications.
• Separate Master Clock outputs for both transmit and receive channels support a clock
up to 512 times the I
2
S sampling frequency.
• Word Select period in master mode is configurable (separately for I
2
S input and I
2
S
output).
• Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for
receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the General Purpose DMA block.
• Controls include reset, stop and mute options separately for I
2
S input and I
2
S output.
UM10360
Chapter 20: LPC176x/5x I2S
Rev. 3 — 19 December 2013 User manual