NXP Semiconductors LPC1768 - Isb; Syntax; Operation; Condition Flags

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User manual Rev. 3 — 20 December 2013 720 of 841
NXP Semiconductors
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Chapter 34: Appendix: Cortex-M3 user guide
34.2.10.5 ISB
Instruction Synchronization Barrier.
34.2.10.5.1 Syntax
ISB{cond}
where:
cond is an optional condition code, see Section 34.2.3.7 “
Conditional execution”.
34.2.10.5.2 Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the
ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
34.2.10.5.3 Condition flags
This instruction does not change the flags.
34.2.10.5.4 Examples
ISB ; Instruction Synchronisation Barrier