UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 751 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
– there is no pending exception with sufficient priority to be serviced
– the completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had
before the interrupt occurred. See Section 34.3.3.7.2
for more information.
• Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception
entry, the stack pop is skipped and control transfers to the new exception handler.
• Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during
state saving for a previous exception, the processor switches to handle the higher
priority exception and initiates the vector fetch for that exception. State saving is not
affected by late arrival because the state saved is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late
arriving exception until the first instruction of the exception handler of the original
exception enters the execute stage of the processor. On return from the exception
handler of the late-arriving exception, the normal tail-chaining rules apply.
34.3.3.7.1 Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and
either:
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case
the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask
registers, see Section 34.3.1.3.6
. An exception with less priority than this is pending but is
not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a
late-arriving exception, the processor pushes information onto the current stack. This
operation is referred as stacking and the structure of eight data words is referred as
stack frame. The stack frame contains the following information:
• R0-R3, R12
• Return address
• PSR
• LR.
Immediately after stacking, the stack pointer indicates the lowest address in the stack
frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word
address. If the STKALIGN bit of the Configuration Control Register (CCR) is set to 1,
stack align adjustment is performed during stacking.
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