UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 447 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
19.8.6 I
2
C Data buffer register (I2DATA_BUFFER: I
2
C0, I2CDATA_BUFFER -
0x4001 C02C; I
2
C1, I2C1DATA_BUFFER- 0x4005 C02C; I
2
C2,
I2C2DATA_BUFFER- 0x400A 002C)
In monitor mode, the I
2
C module may lose the ability to stretch the clock if the ENA_SCL
bit is not set. This means that the processor will have a limited amount of time to read the
contents of the data received on the bus. If the processor reads the I2DAT shift register, as
it ordinarily would, it could have only one bit-time to respond to the interrupt before the
received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only I2DATA_BUFFER
register will be added. The contents of the 8 MSBs of the I2DAT shift register will be
transferred to the I2DATA_BUFFER automatically after every 9 bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have 9
bit transmission times to respond to the interrupt and read the data before it is overwritten.
The processor will still have the ability to read I2DAT directly, as usual, and the behavior of
I2DAT will not be altered in any way.
Although the I2DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
19.8.7 I
2
C Slave Address registers (I2ADR0 to 3: I
2
C0, I2C0ADR[0, 1, 2, 3]-
0x4001 C0[0C, 20, 24, 28]; I
2
C1, I2C1ADR[0, 1, 2, 3] - address
0x4005 C0[0C, 20, 24, 28]; I
2
C2, I2C2ADR[0, 1, 2, 3] - address
0x400A 00[0C, 20, 24, 28])
These registers are readable and writable and are only used when an I
2
C interface is set
to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If these registers contain 0x00, the I
2
C will not acknowledge any address on the bus. All
four registers will be cleared to this disabled state on reset.
Table 389. I
2
C Data buffer register (I2DATA_BUFFER: I
2
C0, I2CDATA_BUFFER -
0x4001 C02C; I
2
C1, I2C1DATA_BUFFER- 0x4005 C02C; I
2
C2, I2C2DATA_BUFFER-
0x400A 002C) bit description
Bit Symbol Description Reset
value
7:0 Data This register holds contents of the 8 MSBs of the I2DAT shift register. 0
31:8 - Reserved. The value read from a reserved bit is not defined. NA
Table 390. I
2
C Slave Address registers (I2ADR0 to 3: I
2
C0, I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C,
20, 24, 28]; I
2
C1, I2C1ADR[0, 1, 2, 3] - address 0x4005 C0[0C, 20, 24, 28]; I
2
C2,
I2C2ADR[0, 1, 2, 3] - address 0x400A 00[0C, 20, 24, 28]) bit description
Bit Symbol Description Reset
value
0 GC General Call enable bit. 0
7:1 Address The I
2
C device address for slave mode. 0x00
31:8 - Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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