UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 169 of 841
NXP Semiconductors
UM10360
Chapter 10: LPC176x/5x Ethernet
10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214)
The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214.
Table 169
lists the bit definitions of the register. Details of Hash filter table use can be
found in Section 10.17.10 “
Receive filtering” on page 199.
10.14 Module control register definitions
10.14.1 Interrupt Status Register (IntStatus - 0x5000 0FE0)
The Interrupt Status register (IntStatus) is a read-only register with an address of
0x5000 0FE0. The interrupt status register bit definition is shown in Table 170
. Note that
all bits are flip-flops with an asynchronous set in order to be able to generate interrupts if
there are wake-up events while clocks are disabled.
Table 169. Hash Filter MSBs register (HashFilterH - address 0x5000 0214) bit description
Bit Symbol Function Reset
value
31:0 HashFilterH Bits 63:32 of the imperfect filter hash table for receive
filtering.
0x0
Table 170. Interrupt Status register (IntStatus - address 0x5000 0FE0) bit description
Bit Symbol Function Reset
value
0 RxOverrunInt Interrupt set on a fatal overrun error in the receive queue. The
fatal interrupt should be resolved by a Rx soft-reset. The bit is not
set when there is a nonfatal overrun error.
0
1 RxErrorInt Interrupt trigger on receive errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
0
2 RxFinishedInt Interrupt triggered when all receive descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
0
3 RxDoneInt Interrupt triggered when a receive descriptor has been processed
while the Interrupt bit in the Control field of the descriptor was set.
0
4 TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The
fatal interrupt should be resolved by a Tx soft-reset. The bit is not
set when there is a nonfatal underrun error.
0
5 TxErrorInt Interrupt trigger on transmit errors: LateCollision,
ExcessiveCollision and ExcessiveDefer, NoDescriptor or
Underrun.
0
6 TxFinishedInt Interrupt triggered when all transmit descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
0
7 TxDoneInt Interrupt triggered when a descriptor has been transmitted while
the Interrupt bit in the Control field of the descriptor was set.
0
11:8 - Unused 0x0
12 SoftInt Interrupt triggered by software writing a 1 to the SoftintSet bit in
the IntSet register.
0
13 WakeupInt Interrupt triggered by a Wake-up event detected by the receive
filter.
0
31:14 - Unused 0x0
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