UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 440 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
19.8 Register description
Each I
2
C interface contains 16 registers as shown in Table 383 below.
Remark: In the LPC176x/5x, the following registers have been added to support response
to multiple addresses in Slave mode and a new Monitor mode: I2ADR1 to 3, I2MASK0 To
3, MMCTRL, and I2DATA_BUFFER.
Table 383. I
2
C register map
Generic
Name
Description Access Reset
value
[1]
I
2
Cn Name & Address
I2CONSET I2C Control Set Register. When a one is written to
a bit of this register, the corresponding bit in the I
2
C
control register is set. Writing a zero has no effect on
the corresponding bit in the I
2
C control register.
R/W 0x00 I2C0CONSET - 0x4001 C000
I2C1CONSET - 0x4005 C000
I2C2CONSET - 0x400A 0000
I2STAT
I2C Status Register. During I
2
C operation, this
register provides detailed status codes that allow
software to determine the next action needed.
RO 0xF8 I2C0STAT - 0x4001 C004
I2C1STAT - 0x4005 C004
I2C2STAT - 0x400A 0004
I2DAT
I2C Data Register. During master or slave transmit
mode, data to be transmitted is written to this
register. During master or slave receive mode, data
that has been received may be read from this
register.
R/W 0x00 I2C0DAT - 0x4001 C008
I2C1DAT - 0x4005 C008
I2C2DAT - 0x400A 0008
I2ADR0
I2C Slave Address Register 0. Contains the 7-bit
slave address for operation of the I
2
C interface in
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
R/W 0x00 I2C0ADR0 - 0x4001 C00C
I2C1ADR0 - 0x4005 C00C
I2C2ADR0 - 0x400A 000C
I2SCLH
SCH Duty Cycle Register High Half Word.
Determines the high time of the I
2
C clock.
R/W 0x04 I2C0SCLH - 0x4001 C010
I2C1SCLH - 0x4005 C010
I2C2SCLH - 0x400A 0010
I2SCLL
SCL Duty Cycle Register Low Half Word.
Determines the low time of the I
2
C clock. I2nSCLL
and I2nSCLH together determine the clock
frequency generated by an I
2
C master and certain
times used in slave mode.
R/W 0x04 I2C0SCLL - 0x4001 C014
I2C1SCLL - 0x4005 C014
I2C2SCLL - 0x400A 0014
I2CONCLR
I2C Control Clear Register. When a one is written
to a bit of this register, the corresponding bit in the
I
2
C control register is cleared. Writing a zero has no
effect on the corresponding bit in the I
2
C control
register.
WO NA I2C0CONCLR - 0x4001 C018
I2C1CONCLR - 0x4005 C018
I2C2CONCLR - 0x400A 0018
MMCTRL
Monitor mode control register. R/W 0x00 I2C0MMCTRL - 0x4001 C01C
I2C1MMCTRL - 0x4005 C01C
I2C2MMCTRL - 0x400A 001C
I2ADR1
I2C Slave Address Register 1. Contains the 7-bit
slave address for operation of the I
2
C interface in
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
R/W 0x00 I2C0ADR1 - 0x4001 C020
I2C1ADR1 - 0x4005 C020
I2C2ADR1 - 0x400A 0020
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