UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 255 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
USBDevIntSt) occurs.
11.14.2 Data transfer for OUT endpoints
When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the
USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,
and set the PKT_RDY bit (Table 216
).
Software can now start reading the data from the USBRxData register (Table 215
). When
the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is set in
the USBDevSt register. Software now issues a Clear Buffer (refer to Table 250
) command.
The endpoint is now ready to accept the next packet. For OUT isochronous endpoints, the
next packet will be received irrespective of whether the buffer has been cleared. Any data
not read from the buffer before the end of the frame is lost. See Section 11.16 “
Double
buffered endpoint operation” for more details.
If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.
11.14.3 Data transfer for IN endpoints
When writing data to an endpoint buffer, WR_EN (Section 11.10.5.5 “USB Control register
(USBCtrl - 0x5000 C228)”) is set and software writes to the number of bytes it is going to
send in the packet to the USBTxPLen register (Section 11.10.5.4
). It can then write data
continuously in the USBTxData register.
When the number of bytes programmed in USBTxPLen have been written to USBTxData,
the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt register.
Software issues a Validate Buffer (Section 11.12.14 “
Validate Buffer (Command: 0xFA,
Data: none)”) command. The endpoint is now ready to send the packet. For IN
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the
next frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.
11.15 DMA operation
In DMA mode, the DMA transfers data between RAM and the endpoint buffer.
The following sections discuss DMA mode operation. Background information is given in
sections Section 11.15.2 “
USB device communication area” and Section 11.15.3
“Triggering the DMA engine”. The fields of the DMA Descriptor are described in
Section 11.15.4 “
The DMA descriptor”. The last three sections describe DMA operation:
Section 11.15.5 “
Non-isochronous endpoint operation”, Section 11.15.6 “Isochronous
endpoint operation”, and Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode
operation”.
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