UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 537 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.10 MCPWM Capture Registers
25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 - 0x400B 8044, 0x400B 8048,
0x400B 804C)
The MCCAPCON register (Table 458) allows software to select any edge(s) on any of the
MCI0-2 inputs as a capture event for each channel. When a channel’s capture event
occurs, the current TC value for that channel is stored in its read-only Capture register.
These addresses are read-only, but the underlying registers can be cleared by writing to
the CAP_CLR address
25.7.10.2 MCPWM Capture clear address (MCCAP_CLR - 0x400B 8074)
Writing ones to this write-only address clears the selected CAP register(s).
Table 477. MCPWM Capture read addresses (MCCAP0/1/2 - 0x400B 8044, 0x400B 8048, 0x400B 804C) bit description
Bit Symbol Description Reset value
31:0 CAP0/1/2 TC value at a capture event for channels 0, 1, 2. 0x0000 0000
Table 478. MCPWM Capture clear address (CAP_CLR - 0x400B 8074) bit description
Bit Symbol Description
0 CAP_CLR0 Writing a 1 to this bit clears the MCCAP0 register.
1 CAP_CLR1 Writing a 1 to this bit clears the MCCAP1 register.
2 CAP_CLR2 Writing a 1 to this bit clears the MCCAP2 register.
31:3 - Reserved
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